1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory, and particularly it relates to a semiconductor memory device with an accelerated operating speed.
2. Description of the Related Art
Conventional semiconductor memory devices such as a synchronous dynamic random access memory (SDRAM) are generally provided with a pre-charge circuit for pre-charging of I/O lines to which a plurality of bit lines pairs connected to memory cells are connected via a column selecting circuit. The pre-charge circuit used here adjusts the I/O lines to a prescribed potential for reading and writing of data, and it accelerates data reading and writing while preventing write and read errors. FIG. 1 is a circuit diagram of a pre-charge circuit in a conventional semiconductor memory device.
In the pre-charge circuit 101 of a conventional semiconductor memory device there are provided two P-channel transistors Tr101a and Tr101b with their drains connected to I/O lines IOT and ION, respectively. A constant voltage Vc is supplied to the sources of the transistors Tr101a and Tr101b, and a pre-charge control signal PIO is supplied to each gate. During pre-charge, both the transistors Tr101a and Tr101b are switched on, and the potentials of the I/O lines IOT and ION become the constant voltage Vc. A design includes an equalizing transistor provided in the pre-charge circuit, with the two I/O lines IOT and ION short-circuited by the equalizing transistor during pre-charge, and adjusted to be at the same potential (balance level).
Operation of a conventional semiconductor device with a pre-charge circuit having that construction will now be explained. FIG. 2A and FIG. 2B are schematics showing the operation of a conventional semiconductor memory device, where FIG. 2A is a timing chart for a case where the constant voltage Vc, i.e. balance level (Vcc/2 less than Vc1 (=Vc) less than Vcc) is high (hereinafter, first prior art), and FIG. 2B is a timing charge for a case where the constant voltage Vc2 is xc2xd of the power voltage Vcc (hereinafter, second prior art). Here, the voltage Vcc is a power voltage supplied to the I/O circuit (not shown) connected to the pre-charge circuit. xe2x80x9cBalance levelxe2x80x9d refers to a potential supplied to the I/O lines IOT and ION through each of the transistors Tr101a and Tr101b, or a potential of the I/O lines IOT and ION that converge when the two I/O lines IOT and ION are short-circuited by the equalizing transistor (not shown).
As shown in FIG. 2A, when the constant voltage Vc is set to satisfy Vcc/2 less than Vc1 less than Vcc (first prior art), the pre-charge control signal PIO is high during pre-charge before writing and reading, and the I/O lines IOT and ION are pre-charged to the voltage Vcl.
Next, when the pre-charge control signal PIO falls to begin writing or reading, the potential of the I/O lines IOT and ION is dragged to the potential of the bit line pairs connected to the memory cells composing a column selected by an address signal. As a result, the potential of the I/O line IOT increases (or decreases) and the potential of the I/O line ION decreases (or increases) in response to the read/written data. That is, a signal fed to the I/O line IOT and a signal fed to the I/O line ION are in a complementary relationship. If the operation at that time is data writing, a written signal is amplified by a write amplifier (not shown), and therefore the increase and decrease of each potential is large. Then, the potential of one I/O line converges to the internal power voltage Vcc, and the potential of the other I/O line converges to the ground potential GND.
On the other hand, if the operation is data reading, bit lines pairs of a DRAM are normally pre-charged to Vcc/2, and immediately after reading the bit line pairs undergo spreading of a potential difference centered on Vcc/2 in response to the read data. However, since amplification by a sense amplifier (not shown) of the differential potential between the bit line pairs is insufficient, the difference between the potential of one bit line pair and the potential of the I/O line IOT (or ION) is small and the increase (or decrease) of the potential of the I/O line IOT (or ION) is small. In contrast, since the voltage Vc1 at the pre-charge level is higher than Vcc/2, the difference between the potential of the other bit line and the potential of the I/O line ION (or IOT) is large. Therefore, the potential of the I/O line ION (or IOT) undergoes a large decrease (or increase). It is therefore possible to obtain a sufficient differential potential for the I/O lines IOT and ION. This is because the relationship between the voltage between the gate-source and the drain current is a square relationship, and therefore a large potential difference between the gate-source results in a greater change in the drain current.
When the pre-charge control signal PIO rises next, the I/O lines IOT and ION are pre-charged to voltage Vc1. The data writing and reading and the pre-charging are then carried out alternately in synchronization with the rise and fall of the pre-charge control signal PIO. Upon completion of reading and writing, the pre-charge control signal PIO is fixed high.
On the other hand, when the constant voltage Vc is set to the voltage Vc2 which is Vcc/2, as shown in FIG. 2B (second prior art), the pre-charge control signal PIO is high during pre-charge before writing and reading, and the IO lines IOT and ION are pre-charged to the voltage Vc2.
Next, when the pre-charge control signal PIO falls to begin writing or reading, the potential of the I/O lines IOT and ION is dragged to the potential of the bit line pairs connected to the memory cells composing a column selected by an address signal. As a result, the potential of the I/O line IOT increases (or decreases) and the potential of the I/O line ION decreases (or increases) in response to the read/write data. If the operation at that time is data writing, a written signal is amplified by the write amplifier (not shown), and therefore the increase and decrease of each potential is large. Then, the potential of one I/O line IOT or ION converges to the internal power voltage Vcc, and the potential of the other I/O line ION or IOT coverages to the ground potential GND. On the other hand, if the operation is data reading, the sense amplification by the sense amplifier (not shown) of the differential potential between the bit line pairs is insufficient, the difference between the potential of both bit lines and the potential of the I/O lines IOT and ION is small and the increase of the potential of the I/O lines IOT and ION is small.
When the pre-charge control signal PIO rises next, the I/O lines IOT and ION are pre-charged to voltage Vc2. At this time, since the pre-charge level is set to Vcc/2, the potential of the I/O lines IOT and ION rapidly reaches the voltage Vc2. The data writing and reading and the pre-charging are then carried out alternately in synchronization with the rise and fall of the pre-charge control signal PIO. Upon completion of reading and writing, the pre-charge control signal PIO is fixed high.
However, in the semiconductor memory device of the first prior are explained above, the constant voltage Vc is set to the voltage Vc1 (Vcc/2 less than Vc1 less than Vcc), and therefore upon pre-charging of the I/O line IOT or ION switched to the GND side immediately after a wiring operation, time is required to restore it to the pre-charge level Vc1. Because of the long restoration time tb, the period of activation of the pre-charge control signal PIO (the high period in FIG. 2A) must be set longer, and thus the time for a single cycle tck for the pre-charge control signal PIO must be set longer.
Conversely, as in second prior art, the problem when the constant voltage Vc is set to voltage Vc2 (Vcc/2) is as follows. When a row address is sent from the outside to the semiconductor memory device, one word line is activated and data stored in a memory cell is outputted via a bit line pair. The sense amplifier amplifies the differential potential of the bit line pair, and discerns the memory data while outputting the discernment results to the I/O line.
However, when amplification by the sense amplifier immediately after the start of reading is insufficient, there is substantially no differential potential between the bit line and the I/O line IOT or ION, so that the differential potential xcex94V produced between the I/O line IOT and the I/O line ION is extremely small. In the case of successive reading of multiple memory cells connected to one word line, such as burst reading, the differential potential xcex94V of the initially read data is the smallest, while the differential potential xcex94V increases with subsequent data. An output buffer begins reading while the differential potential xcex94V is extremely small, and this may inhibit the normal reading operation.
The problem is that, in order to prevent this situation, it is necessary to lengthen the time from initial sensing to initial reading, i.e. the time from input of the row address strobe signal (RAS) until input of the column address strobe signal (CAS) (tRCD: RAS-to-CAS delay), so that output of the sense amplifier can sufficiently amplify the reading data. This has resulted in the problem of a longer time from access of the semiconductor memory device until read out of the data (access time).
Specifically, while the first prior art has the problem of a longer continuous writing time, it allows shortening of the initial reading time. Conversely, the second prior art has the problem of a longer initial reading time, but allows shortening of the continuous writing time.
In a conventional semiconductor memory device, therefore, product specifications have been designed to favor one property while sacrificing the other property. That is, the pre-charge level has been selected and set by either favoring the initial reading time or favoring the continuous writing time. Hence, it has not been possible to shorten both of these times simultaneously. Even with an accelerated clock signal, the speed cannot be fully reached.
It is an object of the present invention to provide a semiconductor memory device that can shorten both the pre-charge control signal cycle and the time from the initial sensing to the first reading or writing.
A semiconductor memory device according to the present invention comprises a memory cell array, a plurality of bit line pairs to which a plurality of memory cells are commonly connected, an I/O line pair to which the plurality of bit line pairs are commonly connected, and a pre-charge circuit which pre-charges the I/O line pair. The plurality of memory cells compose a column in the memory cell array. The pre-charge circuit has a selection circuit which selects a pre-charge level of the I/O line pair from among a plurality of voltage levels.
The selection circuit may set a pre-charge level after a plurality of memory cells are selected up until the initial writing or reading is conducted to a first level, the plurality of memory cells composing a row in the memory cell array of the semiconductor memory device and data writing or reading being performed in the plurality of memory cells. The selection circuit may then set a precharge level after completion of data writing up until the next data writing or reading to a second level.
In the semiconductor memory device according to the present invention a value obtained by the expression |Va-Vbal| may be larger than a value obtained by the expression |Vb-Vbal|, where Va is the first level, Vb is the second level and Vbal is a balance of a differential potential between the I/O line pair at the time of data writing.
In the semiconductor memory device according to the present invention the first level Va may be equivalent to the balance potential Vbal and the second level may be half a voltage supplied to an internal circuit.
The first level may be a voltage obtained by stepping down a voltage supplied to an internal circuit.
The selection circuit may set the pre-charge level to the second level after completion of the second or later data writing or reading after the plurality of memory cells are selected.
According to the present invention, a selection circuit which selects a pre-charge level for the I/O line pair among a plurality of voltage levels is provided in the pre-charge circuit, so that the pre-charge level can be switched during the initial data reading and after data reading. That is, during the initial data reading, the pre-charge level of the I/O line pair is selected by the selection circuit to one with a large difference from the potential of one bit line, thus allowing a large differential potential to be obtained for the I/O line pair. Consequently, if the differential potential of the I/O line pair during the initial data reading is larger and the pre-charge level after data reading is set to allow a balance to be easily achieved, this can be followed even when the clock signal is accelerated. Furthermore, if after data reading the selection circuit sets the pre-charge level of the I/O line pair to be at or near the balance of the differential potential between the I/O line pair at the time of data writing, for example, it is possible to rapidly achieve a balance after the data writing. It is thereby possible to reducing the operating current compared to conventional devices in which the pre-charge level is always set high.